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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
FEATURES
* 2 differential CML outputs * 1 differential LVPECL clock input * IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Output frequency: > 2.5GHz (typical) * Output skew: TBD * Part-to-part skew: TBD * Additive phase jitter, RMS: <100fs (design target) * Propagation delay: 388ps (typical) * Operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V * -40C to 85C ambient operating temperature * Pin compatible with SY58011U
GENERAL DESCRIPTION
The ICS858011 is a high speed 1-to-2 Differentialto-CML Fanout Buffer and is a member of the HiPerClockSTM HiPerClockSTM family of high performance clock solutions from ICS. The ICS858011 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The ICS858011 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications.
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
VCC
IN 1 VT 2
Q0 nQ0
16 15 14 13 12 11 10 9 5
VCC
VCC
VEE
VEE
Q0 nQ0 nQ1 Q1
VREF_AC 3 nIN 4 6
VEE
VEE
Q1 nQ1
VREF_AC
ICS858011
16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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VCC
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IN VT nIN
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8
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
Type Input Input Output Input Power Power Output Output Description Non-inver ting LVPECL differential clock input. Termination input. Reference voltage for AC-coupled applications. VREF_AC = to VCC - 1.38V. Inver ting differential LVPECL clock input. Positive supply pins. Negative supply pin. Differential output pair. CML interface levels. Differential output pair. CML interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 8, 13, 16 6, 7, 14, 15 9, 10 11, 12 Name IN VT VREF_AC nIN VCC VEE Q1, nQ1 nQ0, Q0
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
4.6V (CML mode, VEE = 0) -0.5V to VCC + 0.5 V 20mA 40mA 50mA 100mA 0.5mA -65C to 150C 51.5C/W (0 lfpm) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Input Current, IN, nIN VT Current, IVT Input Sink/Source, IREF_AC Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V
Symbol VCC I EE Parameter Positive Supply Voltage Power Supply Current
TO
3.63V; VEE = 0V
Minimum 2.375 Typical 3.3 TBD Maximum 3.63 Units V mA
Test Conditions
TABLE 2B. DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V
Symbol RIN VIH VIL VIN VDIFF_IN IIN Parameter Differential Input Resistance Input High Voltage Input Low Voltage Input Voltage Swing; NOTE 1 Differential Input Voltage Swing Input Current (IN, nIN) (IN, nIN) (IN, nIN) (IN, nIN) 1.2 0 0.15 0.3 35 Test Conditions Minimum Typical 100 VCC VIH - 0.15 2.8 Maximum Units V V V V mA
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing Diagram
TABLE 2C. CML DC CHARACTERISTICS, VCC = 2.375V TO 3.63V; VEE = 0V
Symbol VOH VOUT VDIFF_OUT ROUT Parameter Output High Voltage; NOTE 1 Output Voltage Swing Differential Output Voltage Swing Output Source Impedance Conditions Minimum VCC - 0.020 325 650 40 Typical VCC - 0.010 400 800 50 60 Maximum VCC Units V mV mV
NOTE 1: Outputs terminated with 100 across differential output pair.
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
Condition Minimum Typical >2.5 388 TBD TBD <100 20% to 80% 120 Maximum Units GHz ps ps ps fs ps
TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.63V TO -2.375V OR VCC = 2.375 TO 3.63V; VEE = 0V
Symbol fMAX Parameter Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time
t PD tsk(o) tsk(pp) tjit
tR/tF
All parameters characterized at 1GHz unless otherwise noted. RL = 100 after each output pair. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC
CML with Internal Pullup + 3.3V 5% or 2.5V 5% GND VCC Qx
SCOPE
nIN
V
IN
Cross Points
V
Power Supply
-
Float GND VEE
IH
IN
V
IL
nQx
V EE
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
nQx Qx nQy Qy
tsk(o)
PART-TO-PART SKEW
nIN IN nQ0, nQ1 Q0, Q1
tPD
OUTPUT SKEW
VIN
VDIF_IN
VIN, VOUT 400mV (typical)
VDIFF_IN, VDIFF_OUT 800mV (typical)
PROPAGATION DELAY
SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER APPLICATION INFORMATION
LVPECL INPUT
WITH
BUILT-IN 50 TERMINATION INTERFACE (2.5V)
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
2.5V
2.5V
The IN/nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 1A to 1E show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V or 2.5V
2.5V
Zo = 50 Ohm
IN
Zo = 50 Ohm
IN
Zo = 50 Ohm
Zo = 50 Ohm
LVDS
VT nIN
VT nIN
Receiver With Built-In 50 Ohm
2.5V LVPECL
R1 18
Receiver With Built-In 50 Ohm
FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
2.5V
2.5V
FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
2.5V
2.5V
Zo = 50 Ohm
Zo = 50 Ohm
IN
Zo = 50 Ohm
IN
VT nIN
Zo = 50 Ohm
VT nIN
CML - Open Collector
Receiver With Built-In 50 Ohm
CML - Built-in 50 Ohm Pull-up
Receiver With Built-In 50 Ohm
FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm R2 25 VT nIN
2.5V
SSTL
Receiver With Built-In 50
FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V
LVPECL INPUT WITH BUILT-IN 50 TERMINATION INTERFACE (3.3V)
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven
3.3V
3.3V
3.3V
Zo = 50 Ohm
IN
Zo = 50 Ohm
Zo = 50 Ohm
IN
Zo = 50 Ohm
VT nIN
VT nIN
LVDS
Receiver With Built-In 50 Ohm
LVPECL
R1 50
Receiver With Built-In 50 Ohm
FIGURE 2A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVDS DRIVER
FIGURE 2B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
IN
Zo = 50 Ohm
IN
Zo = 50 Ohm
VT nIN
VT nIN
CML- Open Collector
Receiver With Built-In 50 Ohm
CML- Built-in 50 Ohm Pull-Up
Receiver With Built-In 50 Ohm
FIGURE 2C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH OPEN COLLECTOR
FIGURE 2D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY A CML DRIVER WITH BUILT-IN 50 PULLUP
3.3V
3.3V
R1
25
Zo = 50 Ohm
IN
Zo = 50 Ohm
SSTL
VT nIN
R2
25
Receiver With Built-In 50 Ohm
FIGURE 2E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50 DRIVEN BY AN SSTL DRIVER
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
2.5V DIFFERENTIAL INPUT
WITH
To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 3.
2.5V
2.5V
R1 680
IN VT nIN
R2 680
Receiver with Built-In 50 Ohm
FIGURE 3. UNUSED INPUT HANDLING
3.3V DIFFERENTIAL INPUT
WITH
BUILT-IN 50 TERMINATION UNUSED INPUT HANDLING
To prevent oscillation and to reduce noise, it is recommended to have pullup and pulldown connect to true and compliment of the unused input as shown in Figure 4.
3.3V
3.3V
R1 1K
IN VT nIN
R2 1K
Receiver with Built-In 50 Ohm
FIGURE 4. UNUSED INPUT HANDLING
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
couple. This example shows the ICS858011 input driven by a 2.5V LVPECL driver with AC couple. The ICS858011 outputs are CML driver with built-in 50 pull up resistors. In this example, we assume the traces are long transmission line and the receiver is high input impedance without built-in matched load. An external 100 resistor across the receiver input is required.
SCHEMATIC EXAMPLE
Figure 5 shows a schematic example of the ICS858011. This schematic provides examples of input and output handling. The ICS858011 input has built-in 50 termination resistors. The input can directly accept various types of differential signal without AC couple. If AC couple termination is used, the ICS858011 also provides VREF_AC pin for proper offset level after AC
3.3V
3.3V
Zo = 50
+
16 15 14 13
VCC VEE VEE VCC
Zo = 50
R3 100
2.5V
-
3.3V LVPECL
Zo = 50
C5
Zo = 50
1 2 3 4
IN VT VREF_AC nIN
VCC VEE VEE VCC
Q0 nQ0 nQ1 Q1
12 11 10 9
100 Ohm Dif f erential
3.3V
Zo = 50
C6
R1 100
R2 100
U1 ICS858011
5 6 7 8
Zo = 50
R4 100
+
[U1,5]
3.3V
[U1,8]
[U1,13]
[U1,16]
100 Ohm Dif f erential
C1 0.1u
C2 0.1u
C3 0.1u
C4 0.1u
FIGURE 5. ICS858011 APPLICATION SCHEMATIC EXAMPLE
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER RELIABILITY INFORMATION
TABLE 4. JAVS. AIR FLOW TABLE
FOR
16 LEAD VFQFN
JA at 0 Air Flow (Linear Feet per Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5C/W
TRANSISTOR COUNT
The transistor count for ICS858011 is: 109
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
16 LEAD VFQFN
PACKAGE OUTLINE - K SUFFIX
FOR
TABLE 5. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A3 b e ND NE D D2 E E2 L 0.25 0.30 0.25 3.0 1.25 0.50 0.18 0.50 BASIC 4 4 3.0 1.25 0.80 0 0.25 Reference 0.30 MINIMUM 16 1.0 0.05 MAXIMUM
Reference Document: JEDEC Publication 95, MO-220
858011AK
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REV. A NOVEMBER 17, 2004
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS858011
LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-CML FANOUT BUFFER
Marking 811A 811A Package 16 Lead VFQFN 16 Lead VFQFN on Tape and Reel Count 490 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 6. ORDERING INFORMATION
Part/Order Number ICS858011AK ICS858011AKT
The aforementioned trademark. HiPerClockSTM
is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 858011AK
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